The presently disclosed and claimed inventive concept(s) relates to compositions and methods for cleaning integrated circuit substrates, and, more particularly, to compositions and methods comprising a halide anion which are effective in removing photoresist, post etch residue, and/or post planarization residue from substrates comprising copper, low-k dielectric material and metal hardmask, such as TiN, TiNxOy and W.
Devices with critical dimensions on the order of 90 nanometers (nm) have involved integration of copper conductors and low-k dielectrics, and they require alternating material deposition processes and planarization processes. As the technology nodes advance to 45 nm and smaller, the decreasing size of semiconductor devices makes achieving critical profile control of vias and trenches more challenging. Integrated circuit device companies are investigating the use of metal hardmasks to improve etch selectivity to low-k materials and thereby gain better profile control.
In order to obtain high yield and low resistance interconnects, the polymers on the sidewalls and the particulate/polymer residues at the via bottoms that are generated during etching must be removed prior to the next process step. It would be very beneficial if the cleaning solution can also effectively etch the selected hardmask to form an intermediate morphology, e.g., a pulled-back/rounded morphology. A pulled-back/rounded morphology could prevent undercutting the hardmask, which, in turn, could enable reliable deposition of barrier metal, Cu seed layer and Cu filling. Alternatively, fully removing the metal hardmask using the same composition could offer numerous benefits to downstream process steps, particularly chemical mechanical polishing (CMP), by eliminating a need for barrier CMP.
Following almost every step in the fabrication process, e.g., a planarization step, a trenching step, or an etching step, cleaning processes are required to remove residues of the plasma etch, oxidizer, abrasive, metal and/or other liquids or particles that remain and which can contaminate the surface of the device if not effectively removed. Fabrication of advanced generation devices that require copper conductors and low-k dielectric materials (typically carbon-silica or porous silica materials), give rise to the problem that both materials can react with and be damaged by various classes of prior art cleaners.
Low-k dielectrics, in particular, may be damaged in the cleaning process as evidenced by etching, changes in porosity/size, and ultimately changes in dielectric properties. Time required to remove residues depends on the nature of the residue, the process (heating, crosslinking, etching, baking, and/or ashing) by which it is created, and whether batch or single wafer cleaning processes are used. Some residues may be cleaned in a very short period of time, while some residues require much longer cleaning processes. Compatibility with both the low-k dielectric and with the copper conductor over the duration of contact with the cleaner is a desired characteristic.
When TiN, TiNxOy or W is used as an etching hard mask to gain high selectivity to low-k materials during a dry etching process in processing advanced copper/low-k semiconductor devices, effective cleaning compositions that can selectively etch TiN, TiNxOy or W must not only be compatible with copper and the low-k materials, but must also be effective in simultaneously removing polymeric materials and etch residues.
With the continuing reduction in device critical dimensions and continuing needs for production efficiency and device performance, there is a need for improved cleaning compositions.